54 research outputs found
Design of Quantum Circuits for Galois Field Squaring and Exponentiation
This work presents an algorithm to generate depth, quantum gate and qubit
optimized circuits for squaring in the polynomial basis. Further, to
the best of our knowledge the proposed quantum squaring circuit algorithm is
the only work that considers depth as a metric to be optimized. We compared
circuits generated by our proposed algorithm against the state of the art and
determine that they require fewer qubits and offer gates savings that
range from to . Further, existing quantum exponentiation are
based on either modular or integer arithmetic. However, Galois arithmetic is a
useful tool to design resource efficient quantum exponentiation circuit
applicable in quantum cryptanalysis. Therefore, we present the quantum circuit
implementation of Galois field exponentiation based on the proposed quantum
Galois field squaring circuit. We calculated a qubit savings ranging between
to and quantum gate savings ranging between to
compared to identical quantum exponentiation circuit based on existing squaring
circuits.Comment: To appear in conference proceedings of the 2017 IEEE Computer Society
Annual Symposium on VLSI (ISVLSI 2017
General solution of functional equations defined by generic linear-fractional mappings F_1: C^N \to C^N and by generic maps birationally equivalent to F_1
We consider a system of birational functional equations (BFEs) (or
finite-difference equations at w=m \in Z) for functions y(w) of the form:
y(w+1)=F_n(y(w)), y(w):C \to C^N, n=deg(F_n(y)), F_n \in (\bf Bir}(C^N), where
the map F_n is a given birational one of the group of all automorphisms of C^N
\to C^N. The relation of the BFEs with ordinary differential equations is
discussed. We present a general solution of the above BFEs for n=1,\forall N
and of the ones with the map F_n birationally equivalent to F_1: F_n\equiv
V\comp F_1\comp V^{-1}, \forall V \in (\bf Bir}(C^N).Comment: 4 pages, 0 figure
Single-Rail Adiabatic Logic for Energy-Efficient and CPA-Resistant Cryptographic Circuit in Low-Frequency Medical Devices
Designing energy-efficient and secure cryptographic circuits in low-frequency medical devices are challenging due to low-energy requirements. Also, the conventional CMOS logic-based cryptographic circuits solutions in medical devices can be vulnerable to side-channel attacks (e.g. correlation power analysis (CPA)). In this article, we explored single-rail Clocked CMOS Adiabatic Logic (CCAL) to design an energy-efficient and secure cryptographic circuit for low-frequency medical devices. The performance of the CCAL logic-based circuits was checked with a power clock generator (2N2P-PCG) integrated into the design for the frequency range of 50 kHz to 250 kHz. The CCAL logic gates show an average of approximately 48% energy-saving and more than 95% improvement in security metrics performance compared to its CMOS logic gate counterparts. Further, the CCAL based circuits are also compared for energy-saving performance against dual-rail adiabatic logic, 2-EE-SPFAL, and 2-SPGAL. The adiabatic CCAL gates save on an average of 55% energy saving compared to 2-EE-SPFAL and 2-SPGAL over the frequency range of 50 kHz to 250 kHz. To check the efficacy of CCAL to design a larger cryptographic circuit, we implemented a case-study design of a Substitution-box (S-box) of popular lightweight PRESENT-80 encryption. The case-study implementation (2N2P-PCG integrated into the design) using CCAL shows more than 95% energy saving compared to CMOS for the frequency 50 kHz to 125 kHz and around 60% energy saving at frequency 250 kHz. At 250 kHz, compared to the dual-rail adiabatic designs of S-box based on 2-EE-SPFAL and 2-SPGAL, the CCAL based S-box shows 32.67% and 11.21% of energy savings, respectively. Additionally, the CCAL logic gate structure requires a lesser number of transistors compared to dual-rail adiabatic logic. The case-study implementation using CCAL saves 45.74% and 34.88% transistor counts compared to 2-EE-SPFAL and 2-SPGAL. The article also presents the effect of varying tank capacitance in 2N2P-PCG over energy efficiency and security performance. The CCAL based case-study was also subjected against CPA. The CCAL-based S-box case study successfully protects the revelation of the encryption key against the CPA attack, However, the key was revealed in CMOS-based case-study implementation
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